The clock signals 1 and 2 are generated from the non overlapping clock generator. Clock 2 is fed to the Latched comparator while the clock 1 is fed to the D flip flop. When V+ is high and V- is low, ...

This circuit transforms a pulse-width-modulation (PWM) signal into non-overlapping clock signals, whose number depends on the length of a shift register. These clock signals can be used to power up ...